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| EM78P153S otp rom EM78P153S 8-bit micro-controller version 1.4
EM78P153S otp rom specification revision history version content 1 . 1 i n i t i a l v e r s i o n 1.2 cha nge initial i zed re giste r value s , internal rc drift rate, dc and ac electri c al ch ara c teri stic 05/02/2003 1.3 cha nge po wer on reset co ntent 06/25/2003 1.4 add the de vi ce cha r a c teri stic at se ction 6.3 12/31/2003 application note an-0 01 q & a on ice153 s an-0 02 th e set-up timin g and pin ch ange wa ke -u p fun c tion application an-0 03 internal rc oscill ator mod e this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 2 EM78P153S otp rom 1. general description em78p15 3s is an 8 - bit mi crop ro ce ssor with lo w-p o wer an d hig h -speed cmos t e ch nolo g y. it is eq uipp ed with a 1024* 13-bits electrical one tim e programm able re ad o n ly memory (otp-ro m ) within it. it provid es a p r ote c tio n bit to prevent intrusi on o f user? s co de in the otp memo ry as well a s 15 option bits to matc h us er?s requirements . with its otp-rom feature, the em 78p153s offers users a conveni ent wa y of d e velopin g an d verifying their prog ram s . more over, use r devel op ed co de c an be ea sily pro g ram m ed with the elan writer. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 3 EM78P153S otp rom 2. features ? 14-lea d pa ckag es : em78 p153s ? operatin g voltage rang e : 2.3v~5.5v ? available in temperature range: 0 EM78P153S otp rom * 14 pin sop 150mil: em78 p153sn ? the transi e nt point of system freq uen cy betwe en hxt and lxt is aroun d 400 khz. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 5 EM78P153S otp rom 3. pin assignments 1 2 3 4 5 8 9 10 EM78P153S 6 7 11 12 13 14 p5 0 p6 7 p6 6 vd d p 65/osci p 64/osco p 63//rst p5 1 p5 2 p5 3 vss p 60//int p6 1 p 62/ tcc fig . 1 pin assignmen t t a ble 1 pin descrip tion symbol pin no. type fun c tion v d d 4 - powe r su pply . p 6 5 / o s c i 5 i / o * gene ral pu rpose i/o pin. * external clo ck sign al inpu t. * input pin of xt oscill ator. * pull-hig h /op en-drai n * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. p 6 4 / o s c o 6 i / o * gene ral pu rpose i/o pin. * external clo ck sign al inpu t. * input pin of xt oscill ator. * pull-hig h /op en-drai n * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. p 6 3 / / r e s e t 7 i * if set as /reset and rem a in at logic low, the device w ill be under reset. * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. * voltage on /reset must not exceed vdd during the norm a l mode. * internal pull -high is on if defined as /reset. * p63 is input pin only p 6 2 / t c c 8 i / o * gene ral pu rpose i/o pin. * pull-hig h /op en-drai n/pull - down. * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. * external timer/counte r i nput. p 6 1 9 i / o * gene ral pu rpose i/o pin. * pull-hig h /op en-drai n/pull - down. * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. * schmitt trig ger in put duri ng the progra mming mo de p 6 0 / / i n t 1 0 i / o * gene ral pu rpose i/o pin. * pull-hig h /op en-drai n/pull - down. * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. * schmitt trig ger in put duri ng the progra mming mo de. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 6 EM78P153S otp rom * external interrupt pin trig gered by falling edg e. p66, p67 2, 3 i/o * gene ral pu rpose i/o pin. * pull-hig h /op en-drai n. * wa ke up fro m slee p mod e whe n the st atus of the pi n cha nge s. p50~p5 3 1 , 1 4 ~ 1 3 i / o * gene ral pu rpose i/o pin. * pull-down p53 12 i/o * gene ral pu rpose i/o pin. v s s 1 1 - * g r o u n d . this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 7 EM78P153S otp rom 4. function description interrupt co n t r o l l er ro m ins t ruc t ion re gi s t er instr u cti o n dec o d e r r2 al u st a c k ac c r3 r4 o s c i ll a t or /t im in g cont r o l wd t t i me r p r es ca l e r r1( t cc ) ram d a ta & co ntro l b u s os c i os c o / r es et tcc / i n t i/ o po r t 6 io c6 r6 b u il t- i n os c p60 p61 p 62/tcc p 6 3//r e s t p 64/os co p 65/os ci p66 p67 i/ o po r t 5 io c 5 r6 p5 0 p5 1 p5 2 p5 3 fig. 2 functional block diagram 4.1 operational registers 1. r0 (indirect addressing register) r0 i s not a p h y sically impl e m ented regi st er. its majo r functio n is to b e an in dire ct add re ssi ng p o inter. any instructio n using r0 as a pointer, actually acce sse s data poin t ed by the ram select registe r (r 4). 2. r1 (time clock /counter) ? increa se d b y an external sign al ed ge, whi c h is defin ed by te bit (co n t-4) th ro ugh the t cc pin, or by t he inst ru c t ion cy cle clo ck. ? writable a n d rea dabl e as any other re giste r s. ? defined by resetting pab (cont - 3). ? the pres caler is ass i gned to t cc if the pab bit (cont-3) is reset. ? the conte n ts of the pre scaler cou n ter i s cle a r ed onl y when a valu e is written to tcc regi ster. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 8 EM78P153S otp rom 3. r2 (program counter) & sta ck ? dependi ng on the device type, r2 and hardware sta ck are 10-bit wide. the structu r e is depi cted in fig.3. ?1024 u 13 bit s on -chip o t p rom a ddresse s to the re lative p r og rammi ng in stru ction code s. one pro g ra m pag e is 102 4 wo rds lon g . ? r2 is s e t as all "0"s when at reset c o ndition. ? "jmp" instru ction allo ws dire ct loading of the lowe r 1 0 prog ram co unter bits. th us, "jmp" allo ws pc to go to any locatio n within a page. ? "call" instruction l oad s the lo wer 10 b i ts of the pc, and the n pc+1 is pu sh ed in to the stack. thu s , the sub r o u tin e entry add re ss can b e located anywhe r e within a pa ge. ? "ret" ("re tl k", "reti" ) in stru ction l oad s the pr o g ram co unte r with the co ntents of th e to p-level st ac k. ? "add r2,a" allows the co ntents of ?a? to be adde d to the current pc, and the ninth and tenth bits of the pc are cl eared. ? "mov r2,a" allows to load an add re ss from the "a " registe r to the lowe r 8 bits of the pc, and the ninth and tent h bits of the pc are cle a re d . ? any instruct ion that is wri tten to r2 (e. g . "add r2,a", "mov r2,a", "bc r2,6", ? ? ? ? ? ) will cause the ninth and tent h bits (a8,a9) of the pc to be clea re d. thus, the com puted jump is limited to the first 256 lo cation s of a page. ? a ll inst ruct i ons a r e si ngl e inst ru ct io n cy cle (f clk/ 2 or fclk/4 ), except for the i n structio n tha t would cha nge the contents of r2 . this instruct ion will ne ed one mo re in stru ction cy cle. pc ( a 9 ~ a0) stac k level 1 stac k level 3 stac k level 2 stac k level 4 stac k level 5 on-c hip p r ogr a m me m o r y 000h 3ffh 008h fig. 3 program counter organization this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 9 EM78P153S otp rom addr ess r p a ge register s ioc p a ge re gister s 00 r0 r e se rv e 01 r1 ( t cc) co nt (control regi ster) 02 r2 (pc ) r e se rv e 03 r3 (s t a tus ) r e se rv e 04 r4 (rs r ) r e se rv e 05 r5 (port5 ) ioc5 (i/o port control regis t er) 06 r6 (port6 ) ioc6 (i/o port control regis t er) 0 7 r e se r v e re se r v e 0 8 r e se r v e re se r v e 0 9 r e se r v e re se r v e 0 a r e se r v e re se r v e 0 b r e se r v e iocb (pull-do wn registe r) 0 c r e se r v e iocc (op en-drain cont rol) 0 d r e se r v e iocd (pull-high co ntrol regi ster) 0 e r e se r v e ioce (wdt control regi ster) 0f rf (interrupt s t atus) iocf (interrupt ma sk regi ste r ) 10 U fig. 4 dat a memor y configura t ion this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 10 EM78P153S otp rom 4. r3 (status register) 7 6 5 4 3 2 1 0 r s t g p 1 g p 0 t p z d c c ? bit 7 (rst ) bit for res e t type. set to 1 if wake -up fro m sl eep mo de on pin ch ang e set to 0 if wak e up from other reset types ? bit6 ~ 5 (g p1 ~ 0) ge ne ral pu rpo s e read/write bits. ? bit 4 (t) time-out bit. set to 1 with the "slep" and "wdtc" comman d , or durin g power up and re set to 0 by wdt time-out. ? bit 3 (p) power down bit. set to 1 durin g power o n or by a "wdtc" comma nd a nd re set to 0 by a "slep" comm and. ? bit 2 (z) zero flag. set to "1" if th e re sult of an arithmeti c or l ogic o p e r atio n is ze ro. ? bit 1 (d c) a u xiliary carry flag ? bit 0 (c ) carry flag 5. r4 (ram select r e gister) ? bits 7 ~ 6 a r e ge neral-pu r po se read/ write bits. see the co nfiguration of t he data memo ry in fig. 4. ? bits 5 ~ 0 a r e u s ed to sel e ct re giste r s (add re ss: 00 ~06, 0f~2f) in the indire ct a ddressin g mo de. 6. r5 ~ r6 (port 5 ~ port 6) ? r5 and r6 are i/o regi st ers. ? only the lower 4 bits of r5 are avail abl e. ? the uppe r 4 bits of r5 are fixed to 0. ? p63 is input only. 7. rf (interrupt status register) 7 6 5 4 3 2 1 0 - - - - - e x i f i c i f t c i f ?1? m ean s int e rrupt re que st, and ?0? me ans n o interru p t occurs. ? bits 7 ~ 3 not used. ? bit 2 (exif) external interru pt flag. set by falling edge on /int pi n, reset by so ftware. ? bit 1 (icif) port 6 input status ch ang ed interru p t flag. set whe n port 6 input cha nge s, re set by s o ftware. ? bit 0 (tcif ) tcc ove r flo w ing inte rrupt flag. set w hen tcc overfl ows, re set by softwa r e. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 11 EM78P153S otp rom ? rf can b e cleared by inst ru ction but ca nnot be set. ? iocf is the interrupt mask regis t er. ? note that the re sult of rea d ing rf is th e "logic and" of rf and io cf. 8. r10 ~ r2f ? all of these are the 8 - bit gene ral - pu rp ose regi sters. 4.2 special purpose registers 1. a (accumulator) ? internal dat a tran sfer, or instructio n op era nd hol ding ? it cannot be add re ssed. 2. cont (control register) 7 6 5 4 3 2 1 0 - i n t t s t e p a b p s r 2 p s r 1 p s r 0 ? bit 7 not used. ? bit 6 (int) i n terrupt ena b l e flag 0: masked by disi or hard w a r e interru p t 1: enable d by eni/reti instructio ns ? bit 5 (ts) t cc sign al so urce 0: internal in structio n cycl e clo ck, p62 i s a bi-di r e c tion al i/o pin. 1: transitio n o n tcc pin ? bit 4 (te) t cc sign al ed ge 0: increment i f the transitio n from low to high takes pl ace o n tcc pin 1: increment i f the transitio n from high to low take s pla c e on t c c pi n ? bit 3 (pa b ) prescal e r a ssignme n t bit. 0: tcc 1: wdt ? bit 2 (psr2) ~ 0 (psr0) tcc/wdt prescale r bits. psr2 psr1 psr0 tc c rate wd t rate 0 0 0 1 : 2 1 : 1 0 0 1 1 : 4 1 : 2 0 1 0 1 : 8 1 : 4 0 1 1 1 : 1 6 1 : 8 1 0 0 1 : 3 2 1 : 1 6 1 0 1 1 : 6 4 1 : 3 2 1 1 0 1 : 1 2 8 1 : 6 4 1 1 1 1 : 2 5 6 1 : 1 2 8 this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 12 EM78P153S otp rom ? cont regi ster is both rea dable a nd wri t able. 3. ioc5 ~ ioc6 (i/o p o rt control register) ? "1" put the relative i/o pin into high imp edan ce, while "0" defines the rel a tive i/o pin as o u tp ut. ? only the lower 4 bits of io c5 a r e availa ble to be defi ned. ? ioc5 and ioc6 regi sters are both re adabl e and writable. 4. iocb (p ull-do wn c ontrol register) 7 6 5 4 3 2 1 0 - / p d 6 / p d 5 / p d 4 - / p d 2 / p d 1 / p d 0 ? bit 7 not used. 0: enable inte rnal p u ll-d o wn 1: disa ble int e rn al pull-do wn ? bit 6 (/pd6) control bit used to en able the pull-d o wn of p62 pin. ? bit 5 (/pd5) control bit is use d to enabl e the pull-do wn of p61 pin . ? bit 4 (/pd4) control bit is use d to enabl e the pull-do wn of p60 pin . ? bit 3 not used ? bit 2 (/pd2) control bit is use d to enabl e the pull-do wn of p52 pin . ? bit 1 (/pd1) control bit is use d to enabl e the pull-do wn of p51 pin . ? bit 0 (/pd0) control bit is use d to enabl e the pull-do wn of p50 pin . ? iocb regi ster is both rea dable a nd wri t able. 5. iocc (open-drain control register) 7 6 5 4 3 2 1 0 o d 7 o d 6 o d 5 o d 4 - o d 2 o d 1 o d 0 ? bit 7 (od 7 ) cont rol bit is use d to enabl e the open -d rain of p67 pin . 0: disa ble op en-drai n outp u t 1: enable op en-drai n outp u t ? bit 6 (od 6 ) cont rol bit is use d to enabl e the open -d rain of p66 pin . ? bit 5 (od 5 ) cont rol bit is use d to enabl e the open -d rain of p65 pin . ? bit 4 (od 4 ) cont rol bit is use d to enabl e the open -d rain of p64 pin . ? bit 3 not used. ? bit 2 (od 2 ) cont rol bit is use d to enabl e the open -d rain of p62 pin . ? bit 1 (od 1 ) cont rol bit is use d to enabl e the open -d rain of p61 pin . ? bit 0 (od 0 ) cont rol bit is use d to enabl e the open -d rain of p60 pin . ? iocc re gister is both rea dable a nd wri t able. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 13 6. iocd (p ull-high c ontrol register) EM78P153S otp rom 7 6 5 4 3 2 1 0 / p h 7 / p h 6 / p h 5 / p h 4 - / p h 2 / p h 1 / p h 0 ? bit 7 (/ph7) control bit is use d to enabl e the pull-hig h of p67 pin. 0: enable inte rnal p u ll-hi gh 1: disa ble int e rn al pull-hig h ? bit 6 (/ph6) control bit is use d to enabl e the pull-hig h of p66 pin. ? bit 5 (/ph5) control bit is use d to enabl e the pull-hig h of p65 pin. ? bit 4 (/ph4) control bit is use d to enabl e the pull-hig h of p64 pin. ? bit 3 not used. ? bit 2 (/ph2) control bit is use d to enabl e the pull-hig h of p62 pin. ? bit 1 (/ph1) control bit is use d to enabl e the pull-hig h of p61 pin. ? bit 0 (/ph0) control bit used to en able the pull-hi gh of p60 pin. ? iocd re gister is both rea dable a nd wri t able. 7. ioce ( w dt control register) 7 6 5 4 3 2 1 0 wd t e e i s - - - - - - ? bit 7 (w dt e) cont rol bit use d to enabl e watchdo g timer. 0: disa ble wdt. 1: enable wdt. wdte is bot h rea dabl e an d writa b le. ? bit 6 (eis) cont rol bit is use d to defin e the function of p60(/int) pin. 0: p60, bi-direction al i/o pin. 1: /int, external interrupt pin. in this case, the i/o c ont rol bit of p60 (bit 0 of ioc6 ) must b e set to "1". whe n eis is " 0 ", the path of /int is m a sked. wh en ei s is "1", the sta t us of /int pin can al so b e read by way of rea d ing port 6 (r6 ) . refer to fig. 7. eis is both re adabl e and writable. ? bit 5 ~ 0 no t used. 8. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - - e x i e i c i e t c i e ? bit 7 ~ 3 no t used. ? individual interru pt is ena bled by settin g its asso ciat ed co ntrol bit in the iocf to "1". ? global inte rrupt is e nabl ed by the eni in stru ction and i s di sabl ed by the disi instruction. refe r to fig . 9. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 14 ? bit 2 (exie) exif interru pt enable bit. EM78P153S otp rom 0: disabl e exif interru pt 1: enable exif interrupt ? bit 1 (icie) icif interrupt enabl e bit. 0: disabl e icif interrupt 1: enable ici f interrupt ? bit 0 (tcie) tcif interru p t enable bit. 0: disabl e tcif interru pt 1: enable t c i f interrupt ? iocf regi ster is b o th rea dable a nd wri t able. 4.3 tcc/wdt & prescaler there is an 8 - bit counte r a v ailable a s p r escale r for th e tcc o r wdt. the p r e s caler i s avail a b l e for the tcc only or the wdt only at the same time and the pab bit of the cont regi ster is used to determine the pre s cale r assign ment. the psr0 ~ p s r2 bits dete r mi ne th e rati o. the presca ler is cle a re d each time the instructio n is written to tcc und er tcc mod e . the wdt a n d pre s cale r, whe n a ssi gn ed to wdt mode, are cl eared by the ?wdtc? or ?slep? inst ru ction s . fig. 5 depicts the circuit di agram of tcc/wdt. ? r1(t cc) is an 8-bit timer/co unte r . the clo ck sou r ce of tcc ca n be intern al or extern al cl ock input (ed ge sele ct a b le from tcc pin). if tcc signal so urce is from interna l clock, tcc will increa se b y 1 a t every instruct ion cycl e (wit hout pre s cale r). refe rri ng to fig. 5, clk=fo sc/2 or clk=fo sc/4, depen ds on the co de option bit cl k. clk=f o sc/2 is u s ed if cl k bit is "0", a nd clk=f o sc/4 is u s ed if clk bit is "1". if tcc sign al so urce is from extern al clo ck inp u t, tcc is in cre a se d by 1 at every falling e dge or risi ng ed ge of tcc pi n. ? the watchd og timer is a free ru nnin g on-chip rc oscillato r . the wdt will kee p runnin g even when the oscillato r driv er ha s be en t u rn ed of f (i.e. in slee p mo de). durin g n o rmal o p e r ati on or slee p mode, a wdt time-ou t (if enable d ) will cau s e the device to reset. the wdt can be en abl ed or disa ble d any time duri ng n o rmal m ode by sof t ware pro g ra mming . refer to wdte bit of ioce regi ster . withou t pre s cale r , the wdt time -o ut perio d is a pproximately 18 ms 1 (defaul t). 4.4 i/o ports the i/o regi sters, both port 5 and port 6, are bi-dir e c ti onal tri-state i/o ports. port 6 can be p u ll ed-high 1 EM78P153S otp rom intern ally by softwa r e except p63. in a ddition, port 6 can also h a ve open-dra i n output by softwa r e except p63. input status ch ange d inte rru p t (or wake-u p) function is available fro m port 6. p50 ~ p52 and p60 ~ p62 pins ca n be pulled-do wn by softwa r e. ea ch i/o pin can be defined as "input" or "ou t put" pin by the i/o co n t rol regi ster (ioc5 ~ io c6 ) except p6 3. t he i/o re gist e r s and i/o co n t rol regi sters are both rea dabl e and writa b le. the i/o interface circuit s for po rt 5 and port 6 are sho w n i n fig. 6,fig.7 and fig. 8 res p ec tively. da ta b u s tcc pi n clk( fosc/ 2 or fo sc/ 4 ) 0 1 m u x m u x 1 0 sync 2 cycl es tcc( r1) te ts pab tcc o v er f l ow i nt er r upt pab pab 0 1 m u x wdt wdt e (in ioc e ) mux w d t ti me o ut 8- bi t count er 8- t o - 1 m u x psr0~psr2 01 fig. 5 block diagram of tcc and wdt this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 16 pc w r p crd pd w r p drd io d 0 1 m u x po r t q q _ d d q q _ clk p r c l clk p r c l EM78P153S otp rom this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 17 *pull-down is not shown in the figure . fig. 6 the circuit of i/o port and i/o c ontrol regis t er for port 5 p crd io d pc w r pd w r p drd bi t 6 o f i o c e po r t t1 0 m u x 0 1 cl k cl k cl k cl k p p p p r r r r c l l l l c c c q q q q q q q q d d d d _ _ _ _ *pull-high (d own), open-drain are no t shown in t he figure. fig. 7 the circuit of i/o port and i/o control regist er for p60(/int) pcw r pdw r pdrd ti n io d port 0 1 m u x clk clk clk p p p l l l r r r c c c d d d q q q q q q _ _ _ EM78P153S otp rom this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 18 *pull-high (d own), open-drain are no t shown in t he figure. fig. 8 the circuit of i/o port and i/o c ontrol regis t er for p61 ~ p 67 / s lep in t err u p t e n i in st ru c t i o n d i si in st ru ct i o n in t erru pt (w a k e - u p f r o m s l e e p ) n e x t in st ru ct i o n ( w a k e - u p f r o m s l eep) cl k cl k cl k q q q q q q _ _ _ d d d p p p l l l r r r c c c ic if p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 fig. 9 b l ock diagram of i/o port 6 w i t h input change interrupt/ w ake-up EM78P153S otp rom table 2 u s age of port 6 i nput change w ake-up/interrupt functi on usage of port 6 input status ch ang e wa ke -up/interru p t (i) wa ke -u p from port 6 inp u t status cha nge (ii) port 6 input status cha nge interrupt (a) before sleep 1. read i/o port 6 (mov r6,r6) 1. disabl e wdt 2. execute "eni" 2. read i/o port 6 (mov r6,r6) 3. enable inte rru pt (set iocf.1) 3. execute "eni" or "d isi" 4. if port 6 chang e (inte r rupt) 4. enable interrupt (s et iocf.1) 4.5 reset and wake-up 1. reset input status cha nge (1) po we r on re set. (2) /reset pin input "low", or (3) wd t time-out (if ena ble d ). the devi c e is kept in a re set conditio n for a peri o d of approx. 1 8 ms 1 (one o scillator sta r t-u p timer period) after the res e t is detec t ed. once the reset oc c u rs , the f o llowing func t i ons are perf o rmed. refer to fig10.. ? the oscillat o r is runni ng, or will b e started. ? the program counter (r2) is s e t to all "0". ? all i/o port pins a r e confi gured a s inpu t mode (hig h-i m ped an ce st ate). ? the watchd og timer an d pre s cale r are clea re d. ? when po we r is switched on, the uppe r 3 bits of r3 are clea red. ? the bits of the co nt reg i ster a r e set to all "1" exce pt for the bit 6 (int flag ). ? the bits of the iocb re gi ster a r e set to all "1". ? the iocc registe r is clea red. ? the bits of the iocd re gi ster a r e set to all "1". ? bit 7 of the ioce re giste r is set to "1", and bits 4 and 6 are clea red. ? bits 0~2 of rf an d bits 0 ~ 2 of iocf re giste r are cle a re d. 1 EM78P153S otp rom the slee p (p owe r down) mode is attained by execu t ing the ?slep? instru ction. while enteri ng slee p mode, wdt (if enabled ) is clea re d but keep s on runni ng. the controller can b e a w a k en ed by (1) external res e t input on /reset pin, (2) wd t time-out (if ena ble d ), or (3) po rt 6 inp u t status cha nge s (if ena bl ed). the first two ca se s will ca use the em7 8 p153s to re set. the t and p flags of r3 can b e used to determi ne the sou r ce of the reset (wa k e-up). th e la st ca se i s con s i dered the con t inuation of p r ogram executio n an d the global interrupt ("eni" or "d isi" being execu t ed) deci d e s wheth e r or n o t the cont rolle r b r a n ch es to the interrupt vect or follo wi n g wa ke -up. if eni is ex ecute d befo r e sle p , the instructio n wil l begin to execute fro m the address 00 8h after wa ke-u p. if disi is execut ed b e fore slep, the operatio n will re start from the inst ru ction ri ght next to slep after wa ke -up. only one of the ca se s 2 a nd 3 ca n be e nable d befo r e enterin g the slee p mod e . that is, [a] if port 6 i nput stat us chang ed i n terrupt is ena ble d befo r e sle p , wdt mu st be disable d . by softwa r e. ho weve r, the wdt bit in the option re gi s t er r e ma in s en ab le d . h e nce, the em78p15 3s ca n be awakene d only by case 1 or 3. [b] if wdt is e nable d befo r e slep, port 6 input stat us cha nge inte rrupt must b e di sabl ed. hen c e, the em78p15 3s can b e awakened o n ly by ca se 1 o r 2. refe r to the section o n inte rru pt. if port 6 input status changed inte rrup t is used to wake -u p the em78p15 3s (ca s e [a] abo ve), the followin g inst ruction s mu st be executed before slep: mov a, @xxxx1110b ; select wdt presca ler, prescaler mu st set over 1:1 co nt w wdtc ; clear wdt and p r e s caler mov a, @ 0 xxxxx x x b ; d i s able wdt i o w r e mov r6, r6 ; read port 6 mov a, @0000 0x1 x b ; enable port 6 input ch ang e interrupt iow rf eni (or disi) ; enable (o r d i sabl e) gl obal interru pt s l e p ; s l e e p note : 1. after wa king up from the sl eep mo de, wdt is automa t ically ena ble d . the wdt e nable d /disabl ed ope ration afte r wa kin g up from sle ep mo de sh ould b e app rop r iately defined in the softwa r e 2. to avoid a reset fro m o c cu rrin g when the po rt 6 input status cha nge d interrupt ente r s into interrupt vect or o r is used to wa ke -up th e mc u, the wdt prescal e r mu st be set above the 1:1 ratio. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 20 EM78P153S otp rom table 3 the summar y of the initializ ed register v a lues address name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name x x x x c53 c52 c51 c50 po w e r - o n 0 0 0 0 1 1 1 1 /reset and wdt 0 0 0 0 1 1 1 1 n / a i o c 5 w a ke-up from pin ch ang e 0 0 0 0 p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n / a i o c 6 wake-up from pin change p p p p p p p p bit name x x x x p53 p52 p51 p50 po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt p p p p p p p p 0 x 0 5 p 5 wake-up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt p p p p p p p p 0 x 0 6 p 6 wake-up from pin change p p p p p p p p bit name x int ts te pab psr2 psr1 psr0 po w e r - o n 1 0 1 1 1 1 1 1 /reset and wdt 1 0 1 1 1 1 1 1 n / a c o n t wake-up from pin change p 0 p p p p p p bit name - - - - - - - - po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p 0 x 0 0 r 0 ( i a r ) wake-up from pin change p p p p p p p p bit name - - - - - - - - po w e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0 x 0 1 r 1 ( t c c ) wake-up from pin change p p p p p p p p bit name - - - - - - - - po w e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0 x 0 2 r 2 ( p c ) wake-up from pin change p p p p n p p p bit name rst gp1 gp0 t p z dc c po w e r - o n 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p 0 x 0 3 r 3 ( s r ) wake-up from pin change 1 p p t t p p p bit name gp1 gp0 - - - - - - po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p 0 x 0 4 r 4 ( r s r ) wake-up from pin change p p p p p p p p bit name x x x x x ex if icif tc i f po w e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0f r f ( i s r ) w a ke-up from pin ch ang e 0 0 0 0 0 p n p bit name x /pd6 /pd5 /pd4 /pd3 /pd2 /pd1 /pd0 po w e r - o n 1 1 1 1 1 1 1 1 0 x 0 b i o c b /reset and wdt 1 1 1 1 1 1 1 1 this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 21 EM78P153S otp rom address name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake-up from pin change p p p p p p p p bit name od7 od6 od5 od4 x od2 od1 od0 po w e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0 x 0 c i o c c wake-up from pin change p p p p p p p p bit name /ph7 /ph6 /ph5 /ph4 x /ph2 /ph1 /ph0 po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0 x 0 d i o c d wake-up from pin change p p p p p p p p bit name wdt e eis x x x x x x po w e r - o n 1 0 1 1 1 1 1 1 /reset and wdt 1 0 1 1 1 1 1 1 0 x 0 e i o c e w a ke-up from pin ch ang e 1 p 1 1 1 1 1 1 bit name x x x x x ex ie icie tc i e po w e r - o n 1 1 1 1 1 0 0 0 /reset and wdt 1 1 1 1 1 0 0 0 0x0f i o c f w a ke-up from pin ch ang e 1 1 1 1 1 p p p bit name - - - - - - - - po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p 0x10~ 0 x 2f r 1 0 ~ r2f wake-up from pin change p p p p p p p p x: not used. u: un kno w n o r don?t care. -: not defi ned p: previou s value b e fore re set. t: check table 4 n: monitors i n terrupt ope ration statu s ; 1 = ru nnin g ; p = not runni ng 2. /reset configure refer to fig. 10 when the reset bi t in the option word is progra mmed to 0, the external /rese t is ena bled. when prog ram m ed to 1, the internal /r e set is enabl ed, tied to the internal vdd and the pin is defin ed as p63. 3. the status of rst, t, and p of status register a reset c o ndition is initiated by the following event s : 1. a power-o n con d ition, 2. a high-low-high pul se on /reset pin, and 3. watch dog timer time-o ut. the value s of rst, t and p, listed in table 4 are use d to che ck h o e the pro c e ssor wakes u p . table 5 sho w s the events whi c h may a ffect the statu s of rst, t and p. this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 22 EM78P153S otp rom table 4 the values of rs t, t and p after reset re set type rst t p powe r on 0 1 1 /reset during operating mode 0 *p *p /reset wake-up during s l eep mode 0 1 0 wdt duri ng ope r ating mo de 0 0 p wdt wa ke -u p duri ng sle ep mode 0 0 0 wake-up on pin change during sleep mode 1 1 0 *p: previous status b e fore re set table 5 the statu s of rs t, t and p b e ing affec t e d b y ev ents event rst t p powe r on 0 1 1 wdtc in stru ction *p 1 1 wdt time-o u t 0 0 *p slep instru ction *p 1 0 wake-up on pin change during sleep mode 1 1 0 *p: previous value befo r e reset vo lt age det ect o r p o w er- o n res e t wdt e se tu p t i me vdd dq clk clr clk res e t w d t ti m e o u t wd t / r es et os c illat o r fig. 10 block diagram o f contr o ller rese t this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 23 EM78P153S otp rom 4.6 interrupt the em78p1 53s ha s thre e falling-edg e interru pts a s listed bel ow: (1) t c c overf l ow inte rru pt (2) po rt 6 input status cha nge interrupt (3) external interrupt [(p60, /int) pin]. before the port 6 input status ch ang e d interrupt is enabled, rea d ing port 6 (e.g. "mov r 6 ,r6") is necessary. each pin of port 6 will have t h is feature if it s status changes. any pi n configured as output or p60 pin confi gured a s /int, is exclud e d from this fu nction. th e port 6 input status chan ge d interru pt can wa ke up t he em7 8 p15 3 s from slee p mode if po rt 6 is ena bled p r ior to goi ng i n to the slee p mode by executin g slep instructio n. when the chip wa ke s- up, the controller will con t inue to execute the pro g ra m in-li ne if the global interru pt is disa bled. if th e global interrupt is ena ble d , it will branch to the interrupt vect or 00 8h. rf is th e inte rru pt statu s re giste r that re cord s the inte rrupt reques ts in the relative flags /bits . iocf is an interrupt mask regi ster. th e global interrupt is enable d by the eni in stru ction and i s disa bled by the disi instructio n. whe n on e of the interrupt s (e nabl ed ) occu rs, the n e xt instru ctio n will be fet c hed fro m add re ss 0 0 8 h . once in th e interrupt se rvice routin e, the sou r ce of an interrupt can b e dete r mined by polling the fl ag bits in rf . the interru p t flag bit mu st be cl ea re d by instru cti ons b e fore le aving the interrupt se rvi c e routine b e fore inte rrupts are en able d to avoid re cu rsive interrupt s. the flag (except icif bit) in the interrup t status regi st er (rf ) is set rega rdle ss of the status of its mask bit or the execution of eni. note that the outcome of rf will be the logic a n d of rf and iocf (refer to fig. 11). the reti instru ction end s the interrupt routi ne and ena bl es t he global i n terrupt ( the executio n of eni). whe n an inte rru pt is gen erated by t he int instru ction (enabl ed ), the nex t instru ctio n will be fetch ed from a d d r e s s 00 1h . this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 24 in t eni/ dis i io d rf wr i o cf rd io c f w r ir q n ir q m rf rd io c f / r es et /i rqn vcc rf clk clk q q d p r l c _ p r l c q q _ d EM78P153S otp rom this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 25 fig. 1 1 interrupt input ci rcuit 4.7 oscillator 1. oscillator modes the em78p1 53s ca n be o perated in fo ur differe nt osc ill ator mo d e s, su ch a s intern al rc o scill ator mode (irc), external rc oscillato r mo de(e r c), hig h xtal oscill ator mo de(hxt), and l o w xtal oscillato r mode(lxt). use r can sele ct one of them by progra mmi ng ocs1 an d osc2 in the code option regi ster. table 6 d epict s ho w these fou r mod e s a r e defin e d . the up -limite d ope ration freque ncy of crystal/re son a tor on the diffe rent vdds i s listed in ta ble 7. table 6 oscillator modes de fined by osc1 and osc2 mode osc1 osc2 irc(internal rc oscillator mode) 1 1 erc(external rc o scill ator mode) 1 0 hxt(high xtal oscillator mode) 0 1 lxt(low xt al oscillator mode) 0 0 EM78P153S otp rom table 7 the summar y of maximum opera ting spe e ds conditions vdd fx t max . (mhz) 2 . 3 4 . 0 3 . 0 8 . 0 two c y c l es with two c l oc ks 5 . 0 2 0 . 0 2. cry s tal oscillator / ce ramic resonators(xtal) em78p15 3s can b e drive n by an extern al clo ck sig n a l throug h the osci pin a s sho w n in fi g. 12. osci osco EM78P153S ext. clock fig. 12 circuit for exter n al clock in put in most applications, pin o s ci and pin osco ca n be conne cted with a crystal or cerami c re so n a tor to gene rate osci llation. fig. 1 3 depict s su ch circuit. the same thing applie s wh ether it is in the hxt mode o r in th e lxt mode. table 8 p r ov ides t he re co mmend ed val ues of c1 an d c2. since each re son a tor ha s its own attribute, user sh o u ld refer to its specifi c ation for appropri a te values of c1 and c2. rs, a se rial re sisto r , may be necessary for at s t rip c u t crys tal or low frequenc y mode osci osco EM78P153S c1 c2 xtal rs fig. 13 circuit for cry s t a l/reson a to r table 8 c a pacitor selection guide fo r cr y s tal oscillator or ceramic resonators this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 26 EM78P153S otp rom oscillator type freq uen cy m ode freq uen cy c1 (pf ) c2 (pf ) 455 khz 100 ~15 0 100 ~15 0 2.0 mhz 20~40 20~40 ce rami c re sonato r s hxt 4.0 mhz 10~30 10~30 32.768 khz 25 15 100k hz 25 25 lxt 200k hz 25 25 455k h z 2 0 ~ 4 0 2 0 ~ 1 5 0 1 . 0 m h z 1 5 ~ 3 0 1 5 ~ 3 0 2 . 0 m h z 1 5 1 5 cry s tal oscill ator hxt 4 . 0 m h z 1 5 1 5 EM78P153S otp rom osci EM78P153S vcc rext cext fig.14 circuit for exte rnal rc oscillator mode table 9 rc oscillator frequencies cext rext average fo sc 5v,25 q c average fo sc 3v,25 q c 3 . 3 k 3 . 9 2 m h z 3 . 6 3 m h z 5.1k 2.67 mhz 2.6 mhz 10k 1.4 mhz 1.4 mhz 20 pf 100k 150 khz 156 khz 3.3k 1.4 mhz 1.33 mhz 5.1k 940 khz 917 khz 10k 476 khz 480 khz 100 pf 100k 50 khz 52 khz 3.3k 595 khz 570 khz 5.1k 400 khz 384 khz 10k 200 khz 203 khz 300 pf 100k 20.9 khz 20 khz EM78P153S otp rom table 10 inte rnal rc drift rate ( t a= 25 4.8 code option register the em78p1 53s has o ne co de option word that is not a part of the norm a l program memo ry. the option bits ca nnot be a c ce ssed du rin g n o rmal p r o g ra m executio n. cod e option regi ste r and cu stome r id regi ste r arra ngem ent distribution: wo rd 0 wo rd1 wo rd 2 bit12~ b i t 0 b i t 1 ~ b i t 0 bit12~ b i t 0 code option register (word 0 ) word 0 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 /reset /enwdt clks osc1 ocs0 cs sut 1 sut 0 t ype rcout c2 c1 c0 ? bit 12 (/re set ): define pin7 a s a re set pin. 0: /reset enable 1: /reset dis able ? bit 1 1 (/en wt d ): w a tch dog timer e n a b le bit. 0: enable 1: disa ble EM78P153S otp rom lxt(low xt al oscillator mode) 0 0 EM78P153S otp rom 4.9 power on consideratio n s any micro c on troller is not g uarantee d to start to opera t e prope rly before the pow e r sup p ly stabil i ze s at its steady sta t e. under customer ap plica t ion, when po we r is off, v dd must dro p to below 1.8v and remai n s of f for 10us be fore po we r can be switch ed on ag ain . this way, the em78p15 3s will re set and work no rmally. the extra external re set ci rcui t will wo rk well if vdd can rise at very fast spe ed (50 m s o r le ss). however, unde r mo st case s whe r e cr itical a ppli c at ions are i n vol v ed, extra de vices are req u ire d to assist in solving the powe r -up probl ems. 4.10 programmable oscillator set-up time the option word contains sut 0 and sut1 whi c h can be used to define the oscillator set up time. theo rically, the rang e is f r om 4.5 m s to 72 m s . for m o st of crystal or cerami c re son a tors, the lowe r the ope ration fre quen cy is, the longe r the set-up time ma y be requi red. tabl e 12 describ es th e values of oscillator set-up time. 4.11 external power on reset circu i t the ci rcuit sh own i n fig 17 impleme n ts a n external rc to prod uce the re set pul se. the pul se wid t h (time con s tant ) sh o u ld be kept lo ng eno ugh fo r vdd to rea c h minimum o peration volta ge. this ci rcu i t is used when the power supply has slow ri se ti me. because the current leaka ge from the /reset pin is about EM78P153S /reset vdd d r rin c fig. 15 external po w e r-up rese t cir c uit 4.12 residue-voltage protection whe n battery is repl ace d , device p o we r (vd d ) is taken off but re sidu e - voltage rem a ins. th e this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 31 EM78P153S otp rom re sidu e-volta ge may trip s belo w vdd mi nimum, but n o t to zero. thi s conditio n m a y cau s e a p oor p o wer on re set. fig.18 and fi g. 19 sho w ho w to build a resi due -voltage p r ote c tion ci rcuit. e m 78p 153s /r eset vd d 10 0k q1 1n 468 4 10k 33 k vd d fig. 16 circuit 1 for th e residue v o lt a g e protectio n em 7 8 p1 5 3 s / r eset vd d q1 vd d r3 r2 r1 fig.17 circu i t 2 for the r e sidue v o lt ag e prote c tion 4.13 instruction set each inst ru ction in the instru ction set is a 13-bit word divided i n to an op code and on e or more ope ran d s. no rmally, all in structio ns are execute d wit h in on e si ngl e inst ru ction cycle (o ne in stru ction con s i s ts of 2 oscillato r pe ri ods), unle s s the pro g ra m cou n ter i s ch ange d by in structio n "mo v r2,a", this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 32 EM78P153S otp rom "add r2,a", or by instru cti ons of arithm etic or logi c operation on r2 (e.g. "sub r2,a", "bs(c) r2,6", "clr r2", ??? ? EM78P153S otp rom 0 0001 0 0 rr rrrr 01rr sub a,r r-a ? EM78P153S otp rom 4.14 timing diagrams reset timin g ( c lk= " 0") clk / r es et nop in struc t ion 1 e x ecu te d td r h tc c in put timing (clks= "0") clk tc c tt c c ti n s a c t esti ng : inpu t is d r iv en at 2. 4v for lo gic "1 ", and 0 . 4v fo r l ogic "0".t i min g meas u r ement s are made at 2.0v f o r logi c "1", a n d 0. 8 v f o r log i c "0". a c tes t i n put/output wav e form 2.4 0.4 2.0 0.8 t est poi n t s 2. 0 0. 8 this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 35 EM78P153S otp rom 5. absolute maximunm ratings items rating tempe r atu r e unde r bia s 0 storage tem p eratu r e -65 input voltage -0.3v to + 6 .0v output voltag e -0.3v to + 6 .0v this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 36 EM78P153S otp rom 6. electrical characteri s tic 6.1 dc electrical characteristic ( ta= 0 q c ~ 70 q c, vdd= 5.0v r 5 % , vss= 0v ) sy m b o l parameter cond itio n min ty p max unit fx t x t al: vdd to 2.3v t w o c y cle w i th t w o clocks dc 4.0 mhz fx t x t al: vdd to 3v t w o c y cle w i th t w o clocks dc 8.0 mhz fx t x t al: vdd to 5v t w o c y cle w i th t w o clocks dc 20.0 m hz erc r: 5k : , c: 39 pf f - 30 150 0 f+3 0 khz iil input leak ag e current for in p u t pins vin = vdd, vss r 1 p a vih1 input hig h volt age (vdd= 5. 0 v ) ports 5, 6 2.0 v vil1 input lo w vo ltage (vdd= 5. 0 v ) ports 5, 6 0.8 v viht 1 input hig h t h reshol d vo lta g e (vdd=5.0v) / reset, t cc (schmitt trigger ) 2 .0 v vilt 1 input lo w t h reshold v o ltag e (vdd=5.0v) / reset, t cc (schmitt trigger ) 0.8 v vihx1 clock inp u t hig h voltag e (vd d =5.0v) osci 2.5 v vilx1 clock inp u t lo w vo ltag e (vd d = 5 .0v) osci 1.0 v vih2 input hig h volt age (vdd= 3. 0 v ) ports 5, 6 1.5 v vil2 input lo w vo ltage (vdd= 3. 0 v ) ports 5, 6 0.4 v viht 2 input hig h t h reshol d vo lta g e (vdd=3.0v) / reset, t cc (schmitt trigger ) 1 .5 v vilt 2 input lo w t h reshold v o ltag e (vdd=3.0v) / reset, t cc (schmitt trigger ) 0.4 v vihx2 clock inp u t hig h voltag e (vd d =3.0v) osci 1.5 v vilx2 clock inp u t lo w vo ltag e (vd d = 3 .0v) osci 0.6 v voh1 output high v o ltag e (ports 5, 6) (p60~ p63, p66 ~ p67 are sch m itt trigger) ioh = -12.0 ma 2.4 v vol1 output lo w vo ltage (p5 0 ~ p 5 3 , p60~ p63, p66~ p67), (p6 0 ~ p 63, p66~ p 67 are schmitt trigger) iol = 12.0 ma 0.4 v vol2 output lo w vo ltage (p6 4 ,p 65 ) iol = 16.0 ma 0.4 v iph pull-h i gh c u rre nt pull-h i gh active , input pin at v s s - 50 -100 -240 p a ipd pull-d o w n c u rrent pull-d o w n activ e , input pi n at vdd 20 50 120 p a isb1 po w e r do w n c u rrent all input and i/o pins at vdd, output pi n floati ng, w d t disab l ed 1 p a isb2 po w e r do w n c u rrent all input and i/o pins at vdd, output pi n floati ng, w d t enabl ed 1 0 p a icc1 operatin g sup p l y c u rrent(vd d = 3 v) at t w o clocks /reset= 'high', fosc=32khz (cry stal t y pe,clks="0"), output pi n floati ng, w d t disab l ed 1 5 1 5 3 0 p a icc2 operatin g sup p l y c u rrent (vd d = 3 v) at t w o clocks /reset= 'high', fosc=32khz (cry stal t y pe,clks="0"), output pi n floati ng, w d t enabl ed 1 9 3 5 p a icc3 operatin g sup p l y c u rrent(vd d = 5 .0v) at t w o clocks /reset= 'high', fosc=4mhz (cry stal t y pe, clks="0"), output pi n floati ng 2 . 0 m a icc4 operatin g sup p l y c u rrent(vd d = 5 .0v) at t w o clocks /reset= 'high', fosc=10mhz (cry stal t y pe, clks="0"), output pi n floati ng 4 . 0 m a rc: vdd to 5v * these pa ra meters are ch ara c teri ze s a nd tested. * data in the minimum, typical, maximum(?mi n ?,?typ?, ?max?) colum n are ba se d on cha r a c teri zation re sults at 25 EM78P153S otp rom 6.2 ac electrical characteristic (ta=0 q c ~ 70 q c, vdd=5v r 5 % , vss=0 v ) sy m b o l parameter cond itio ns min ty p max unit dclk input clk dut y c y cle 45 50 55 % cr y s ta l t y p e 100 dc ns ti n s instruction c y cle time (clks="0") rc t y p e 500 dc ns t t cc t cc input peri od (t ins+ 20)/n* ns t d r h d e v i c e re set hold time ta = 2 5 q c tx a l , s u t 1 , s u t0 = 1 , 1 17.6-3 0 % 17.6 17.6+ 30 % ms t r s t / r e s e t p u l s e w i d t h ta = 2 5 q c 200 0 n s t w dt1 * w a tchdog time r period ta = 2 5 q c sut 1 ,su t 0= 1,1 17.6-3 0 % 17.6 17.6+ 30 % ms t w dt2 * w a tchdog time r period ta = 2 5 q c sut 1 ,su t 0= 1,0 4.5-30 % 4 . 5 4.5+ 3 0 % ms t w dt3 * w a tchdog time r period ta = 2 5 q c sut 1 ,su t 0= 0,1 288- 3 0 % 2 8 8 288+ 3 0 % m s t w dt4 * w a tchdog time r period ta = 2 5 q c sut 1 ,su t 0= 0,0 72-3 0 % 7 2 72+ 30 % ms t s et input pin set u p time 0 ns t hold input pin h o l d time 20 ns t dela y output pin d e la y time cloa d = 2 0 p f 50 ns * twdt1: the option word (sut1,sut 0 ) is used to defi ne the oscillat o r set-up time. in crystal mode the wdt timeout lengt h is the sa me as set - up tim e (1 8ms). * twdt2: the option word (sut1,sut 0 ) is used to defi ne the oscillat o r set-up time. in crystal mode the wdt timeout lengt h is the sa me as set - up tim e (4.5m s ). * twdt3: the option word (sut1,sut 0 ) is used to defi ne the oscillat o r set-up time. in crystal mode the wdt timeout lengt h is the sa me as set - up tim e (2 88m s). * twdt4: the option word (sut1,sut 0 ) is used to defi ne the oscillat o r set-up time. in crystal mode the wdt timeout lengt h is the sa me as set - up tim e (7 2ms). * these pa ra meters are ch ara c teri ze s b u t not tested. * data in the minimum, typical, maximum(?mi n ?,?typ?, ?max?) colum n are ba se d on cha r a c teri zation re sults at 25 EM78P153S otp rom 6.3 device characteristic the gra p h s provided in the followi ng pag e s we re deriv e d base d on a limited numbe r of sample s a nd are sho w n here for reference only. th e device ch ar acte risti c illustrated he rei n are n o t gua ra nteed for it a c cu ra cy. in so me gra p h s , the data maybe ou t of the specif ied wa rranted operating ra nge. vih/vil (input pins with schmitt inverter) 0 0. 5 1 1. 5 2 2 . 5 3 3 .5 4 4 .5 5 5 .5 vdd (volt) vih vil (volt) vih max (- 40 fig. 18 vih, vil of p 60~p63, p66, p67 v s . vdd this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 39 v t h ( i n put t h e r s h ol d vol t a g e ) o f i / o pi ns 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2 2. 2 2 . 5 3 3. 5 4 4. 5 5 5 . 5 vd d ( v o l t ) vth (volt) this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 40 fig. 19 vth (th r e s hold v o ltage) of p50 ~ p5 3, p64~p65 v s . vdd vo h / io h (vdd=5 v ) -2 5 -2 0 -1 5 -1 0 -5 0 01 23 45 v oh ( v ol t ) ioh (ma ) vo h / i o h ( vdd= 3 v ) -1 0 -8 -6 -4 -2 0 00 . 5 1 1 . 522 . 5 3 v oh (v ol t ) ioh (ma) vo l/io l ( vdd=5 v ) 0 20 40 60 80 100 012 345 vol (volt) port5 , port6.0~po rt6.3 and EM78P153S otp rom this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 41 port6.6~ port6.7 vol v s . iol , vdd=5v vo l / io l ( vdd=3 v ) 0 10 20 30 40 00 . 5 11 . 5 2 2 . 5 3 vo l ( v o l t) iol (ma) port5, port6.0~por t 6.3 and port6.6~ port6.7 vol v s . iol, vdd= 3v vo l / i ol ( vdd= 5v) 0 20 40 60 80 10 0 12 0 01 2 3 4 5 vo l ( v o l t ) iol (ma) ma x 0 t yp 25 m i n 70 fig. 24 port6 . 4 and port6. 5 vol v s . iol, vdd=5v EM78P153S otp rom this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 42 vo l / io l ( vdd=3 v ) 0 10 20 30 40 50 60 00 . 5 11 . 5 2 2 . 5 3 v o l ( v o l t) iol (ma) ma x 0 t yp 25 m i n 70 fig. 25 port6 . 4 and port6. 5 vol v s . iol, vdd=3v w d t ti m e _ o u t 10 15 20 25 30 35 23 456 vd d ( v o l t ) wdt period (ms) this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 43 fig. 26 wdt time o u t period v s . vdd, perscaler set to 1:1 c e xt = 100pf , t ypi c a l r c o s c f r e que nc y 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 2 . 5 3 3. 5 4 4. 5 5 5 . 5 vd d (v o l t ) fre que nc y (m hz ) this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 44 fig. 27 t y pic a l rc os c frequen c y v s . vdd (cext=1 00pf , temperatu r e at 25 i r c os c f r e q u e n c y ( vdd=5 v ) 0 1 2 3 4 5 6 7 8 9 02 5 5 0 7 0 t e m p er at u r e ( ) frequency (m hz) EM78P153S otp rom this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 45 fig. 29 internal rc osc freq ue nc y v s . tempera t ure, vdd=5v i r c o s c f r e que nc y ( v d d = 3 v ) 0 1 2 3 4 5 6 7 8 9 02 5 5 0 7 0 fig. 30 internal rc osc freq ue nc y v s . tempera t ure, vdd=3v EM78P153S otp rom four con d itio ns exist with t he ope r atin g cu rre nt icc1 to icc4. the s e conditio n s are a s follo ws: icc1: vdd=3 v , fosc=32k hz, 2 cl ocks, wdt disable icc2: vdd=3 v , fosc=32k hz, 2 cl ocks, wdt ena ble icc3: vdd= 5v, fos c = 4 m hz , 2 c l ocks , wdt enable icc4: vdd=5 v , fosc=10 m hz, 2 clo c ks, wdt e nabl e t y pi c a l i c c 1 a nd i c c 2 v s . t e m p e r a t ur e ?? ? ?? ? ? ? ? ?? ? ? ? ? ? ? t e m p er at u r e ( m axi m u m i c c 1 an d i c c 2 vs . t e m p e r at u r e ? ?? ?? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ?3 ? : ? ??3??? ma x i c c 2 ma x i c c 1 this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 46 EM78P153S otp rom fig. 32 maximum operati ng curren t (i cc1 and icc2) v s . tempe r atur e t y pi c a l i c c 3 a nd i c c 4 v s . t e m p e r a t ur e 0. 5 1 1. 5 2 2. 5 3 3. 5 4 0 1 0 2 03 04 05 0 6 07 0 t e mp er at u r e ( ) current (ma) t yp i c c 4 t yp i c c 3 fig. 33 t y pic a l operating curren t (icc3 and icc4) v s . temperature m axi m u m i c c 3 an d i c c 4 vs . t e m p e r at u r e 1 1. 5 2 2. 5 3 3. 5 4 0 1 0 2 03 04 05 0 6 07 0 t e m p er at u r e ( ) current (ma ) ma x i c c 4 ma x i c c 3 fig. 34 maximum operati ng curren t (i cc3 and icc4) v s . tempe r atur e this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 47 EM78P153S otp rom two con d itio ns exist with t he standby current i sb1 and isb2. these conditio n s are a s follo ws: isb1: vdd=5 v , wdt disa ble isb2: vdd= 5v, wdt enable t y pi c a l i s b 1 a nd i s b 2 v s . t e m p e r a t ur e ? ? ?? ? ? ? ? ?? ? ? ? ? ? ? t e m p er at u r e ( m axi m u m i s b 1 an d i s b 2 vs . t e m p e r at u r e ? ? ?? ? ? ? ? ? ?? ? ? ? ? ? ? t e m p er at u r e ( this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 48 EM78P153S otp rom fig. 37 oper ating v o ltage under tempera t ure ra n g e of 0 os c = 4 m h z 0. 5 1 1. 5 2 2. 5 1. 5 2 2 . 5 3 3. 5 4 4 . 5 5 5. 5 6 i (ma) v ma x mi n fig. 38 v-i curv e in ope rating mode, operating frequenc y i s 4m hz os c = 3 2 k hz 0 10 20 30 40 50 60 70 1. 5 2 . 5 3. 5 4 . 5 5. 5 v ( v o lt) i (ua ) max mi n fig. 39 v-i curv e in ope rating mode, operating frequ e ncy is 32k hz this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 49 EM78P153S otp rom appendix package ty pes: otp mcu packag e type pin count packag e size em78p15 3 n p d i p 1 4 3 0 0 m i l em78p15 3 n n s o p 1 4 1 5 0 m i l this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 50 EM78P153S otp rom packag e information 14-l ead plas tic dual in line (pdip) 300 mil this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 51 EM78P153S otp rom 14-l ead plas tic small outline (sop) 150 mil this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 52 EM78P153S otp rom elan ( h ea d q uarte r ) m i croelect r o nics c o r p . , ltd. addres s : no. 1 2 , innov a t i on 1 s t. rd. sc ien c e- ba sed in du stri al p a rk , hs i n ch u ci ty , ta i w an. te le phone : 88 6- 3- 5639977 f a cs imi l e : 886- 3- 5639966 elan ( h .k .) microele ct ronics cor p ., ltd. addre s s : r m . 1005b, 10/ f , em pi r e cent re, 68 mody r o ad, ts im shats u i , kowl oon, hong kong. te le phone : 85 2- 27233376 f a cs imi l e : 852- 27237780 e-mail : ela n h k @emc.co m .h k elan mi cro e lectronics shenzhen, ltd. address : ss m e c bldg . 3f , g a oxin s . ave. 1st , so uth are a , sh enzh en high -t ech indu stri al p a rk., sh enzh en te le phone : 86 - 755- 2601056 5 f a cs imi l e : 86-755- 260105 00 elan mi cro e lectronic s s h ang h ai, ltd. addre s s : #23 buil d i ng n o . 1 1 5 lane 572 bibo r o ad. zhang j i a ng , hi- t e c h park, shanghai te le phone : 86 - 21- 50803866 f a cs imi l e : 86-21- 5080460 0 e l a n i n fo r m at i o n t e c h no l o g y g r o u p . addre s s : 1821 sarat o ga avenue, suit e 250, sarat o ga, c a 95070, u sa te le phone : 1 - 408- 366- 8225 f a cs imi l e : 1- 4 08- 366- 8220 elan mi cro e le ctron i cs c o rp . (eur op e) addre s s : d u b e ndorfs t r as se 4, 8051 zuri c h , swi t ze rl and te le phone : 41 - 43- 2994060 f a cs imi l e : 41-43- 2994079 ema il : inf o @e l a n- eur o pe .co m web-s i t e : w w w.elan -europ e.com copy right ? 2 004 elan mi croele c tro n ics co rp. all rig h ts re se rved. elan own s the intellect ual prope rty righ ts, concept s, idea s, inventions, kno w -ho w (whethe r p a tentable or not) relat ed to the information a n d tech nolo g y (herei n after refe rred as " informa t ion and technol ogy") mention ed a b o ve, and all it s related i ndu st rial pro p e r ty right s thro ug hout the wo rl d, as n o w may exist or to be cre a ted in the future. elan rep r e s ents no wa rra n ty for the us e of the speci f ication s describe d , either expressed or impli e d, includi ng, but not limited, to the implied warranties of mercha ntabili ty and fitness for particular purpo se s. th e entire ri sk a s to the qualit y and perfo rman ce of the applicatio n is with the use r . in no even shall el an be liable for any loss or dama ge to revenue s, profits or g o o d will or othe r spe c ial, inci d ental, i ndire ct and con s e q u ential dama g e s of any kind , resulting from the p e rf orma nce or f a ilure to pe rform, in cludi n g witho u t limitation any int e rruption of busi n e ss, whateve r resulting from b r each of co ntract or b r e a ch of warranty, e v en if elan has be en a d vised of the possibility of such damages. the spe c ifications of the produ ct and its applie d techn o logy will be update d o r ch ange d time b y time. a ll the inform atio n and expl an ations of the produ cts i n th is web s ite is only for your referen c e. t he a c tual spe c ification s and appli ed tech nolo g y wil l be based on each confi r m ed order. elan re se rves the rig h t to modify th e informati o n without prio r notificati on. the most u p -to-day informatio n is available on the web s ite h ttp://www.em c.co m.tw . this specification is subject to cha nge w i thout prio r notice. 4. 1.2004 (v1 . 4) 53 |
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